Computer Address Decoding

About the decoding of computer addresses

A typical address bus in a microcomputer is 16 bits wide, allowing 65 536 separate addresses to be accessed in the range 0000–FFFF (in hexadecimal representation). Special commands on some computers are reserved for accessing the bottom-end 256 of these addresses in the range 0000-OOFF, and, if these commands are used, only 8 bits are needed to specify the required address. For the purpose of explaining address-decoding techniques, the scheme below shows how the lower 8 bits of the 16 bit address line are decoded to identify the unique address referenced by one of these special commands. Decoding of all 16 address lines follows a similar procedure but requires a substantially greater number of integrated circuit chips.


Address decoding is performed by a suitable combination of logic gates. This consists of 256 eight-input NAND gates, which each uniquely decode one of 256 addresses. A NAND gate is a logic element which only gives a logic level 1 output when all inputs are zero, and a logic level 0 output for any other combination of inputs. The inputs to the NAND gates are connected on to the lower eight lines of the address bus and the computer peripherals are connected to the output of the particular gates which decode their unique addresses. There are two pins for each input to the NAND gates which respectively invert and do not invert the input signal.

 

By connecting the eight address lines appropriately to these two alternative pins at each input, the gate is made to decode a unique address. This NAND gate decodes address C5 (hexadecimal) which is 11000101 in binary. Because of the way that the input pins to the chip are connected, the NAND gate will see all zeros at its input when 11000101 is on the lower 8 bits of the address bus and therefore have an output of 1. Any other binary number on the address bus will cause this NAND gate to have a zero output.


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